A conventional MOS transistor generally includes a semiconductor substrate, such as silicon, having a source, a drain, and a channel positioned between the source and drain. A gate stack composed of a conductive material (a gate conductor), an oxide layer (a gate oxide), and sidewall spacers, is typically located above the channel. The gate oxide is typically located directly above the channel, while the gate conductor, generally comprised of polycrystalline silicon (polysilicon) material, is located above the gate oxide. The sidewall spacers protect the sidewalls of the gate conductor.
Generally, for a given electric field across the channel of a MOS transistor, the amount of current that flows through the channel is directly proportional to a mobility of carriers in the channel. Thus the higher the mobility of the carriers in the channel, the more current can flow and the faster a circuit can perform when using high mobility MOS transistors. One mechanism to increase the mobility of the carriers in the channel of an MOS transistor is to produce a mechanical stress or strain in the channel.
A compressive strained channel typically provides hole mobility enhancement, which is particularly beneficial for PMOS devices, whereas a tensile strained channel typically provides electron mobility enhancement, which is particularly beneficial for NMOS devices. An exemplary method of introducing tensile strain in a channel region is to cover transistor devices with a CAP layer comprised of a selected material that, when annealed, generates the tensile strain in the channel regions. An exemplary method of introducing compressive strain in a channel region is to remove a selected amount of material from a surface portion of active regions and subsequently re-depositing a material that generates the appropriate strain.
However, the compressive strain that improves hole mobility can degrade electron mobility and the tensile strain that improves electron mobility can also degrade hole mobility. As a result, introducing tensile strain, such as by using a CAP layer, can improve performance of NMOS devices but degrade performance of PMOS devices. Additionally, introducing compressive strain, such as by recessing and filling with a suitable material, can improve performance of PMOS devices but degrade performance of NMOS devices.